Relaxation

Event Driven Simulators evaluate a design on every event, by taking each event and propagating the changes through design until a steady state condition is reached. An event is defined as a change in any of the input stimuli for a design element. A design element may be evaluated several times in a single cycle because of different arrival times of the inputs and the feedback of signals from downstream design elements. The combinational logic path can have several gates and feedback path. This might take several evaluations before the value stabilizes and no longer change in that clock cycle. This is because event driven simulators provides accurate simulation environment. They evaluate the logic between state elements and/or ports in a single shot. This helps in significant increase in simulation speeds as each logic element is evaluated only once per cycle. The disadvantage is that it cannot really detect any glitches in signals, and it works really well only on logic designs that are fully synchronous. Since timing of design is not taken into account during simulation, separate effort needs to be done on timing verification using any of the static timing analysis tools. Cycle based simulators are not very popular for general designs but are custom made and used at some of the companies that develops large designs like microprocessors. What is a transaction? What are the benefits of Transaction based verification? A transaction is a higher level abstraction of a group of low level information, like a group of signals. While designs operate at signal level information, testbenches need to have drivers and monitors interfacing at signal level with the design, while all other aspects of testbenches can be abstracted to be at a transaction level. Transaction based Verification is an approach in which a testbench is architected in a layered fashion where only lower layered components operate at signal level and all other components operate and communicate based on transactions as shown below. Once these components group signal level information to a transaction, other components like stimulus generators, slave models and scoreboards can all operate on transactions. What all simulation/debug tools have you worked on or are you familiar with? This is a general question to test your awareness on different tools. Based upon your answer and experience with different tools, you could also be asked about your views in terms of easiness/limitations that you might have come across while using these tools. Formal tools include Jasper from Cadence, and QuestaFormal from Mentor graphics. The reference model is sometimes implemented either to match design specification at a cycle level accuracy, or at a higher level boundary. Reference models are normally used in checkers/scoreboards to generate an expected response for a given stimulus pattern so that it can be compared against actual result or the output obtained from the design.

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